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19-3438; Rev 0; 10/04
KIT ATION EVALU E AILABL AV
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
General Description Features
Six (MAX6874) or Four (MAX6875) Configurable Input Voltage Detectors One High Voltage Input (+1.25V to +7.625V or +2.5V to +13.2V Thresholds) One Voltage Input (+1.25V to +3.05V or +2.5V to +5.5V) Four (MAX6874) or Two (MAX6875) Positive Voltage Inputs (+0.5V to +3.05V or +1V to +5.5V) Four (MAX6874) or Three (MAX6875) GeneralPurpose Logic Inputs Two Configurable Watchdog Timers Eight (MAX6874) or Five (MAX6875) Programmable Open-Drain Outputs Active-High or Active-Low Timing Delays from 25s to 1600ms Margining Disable and Manual Reset Controls 4kb Internal User EEPROM Endurance: 100,000 Erase/Write Cycles Data Retention: 10 Years I2C/SMBus-Compatible Serial Configuration/ Communication Interface 1% Threshold Accuracy
MAX6874/MAX6875
The MAX6874/MAX6875 EEPROM-configurable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and general-purpose logic inputs, and provide programmable open-drain outputs for highly configurable power-supply sequencing applications. The MAX6874 provides six voltage monitor inputs, four general-purpose inputs, and eight programmable open-drain outputs. The MAX6875 provides four voltage monitor inputs, three general-purpose inputs, and five programmable open-drain outputs. Manual reset and margin disable inputs provide additional flexibility. All voltage detectors offer configurable thresholds for undervoltage detection. One high-voltage input (IN1) provides detector threshold voltages from +2.5V to +13.2V in 50mV increments, or from +1.25V to +7.625V in 25mV increments. A second positive input (IN2) provides detector threshold voltages from +2.5V to +5.5V in 50mV increments, or from +1.25V to +3.05V in 25mV increments. Positive inputs (IN3-IN6) provide detector threshold voltages from +1V to +5.5V in 20mV increments, or from +0.5V to +3.05V in 10mV increments. Programmable output stages control power-supply sequencing or system resets/interrupts. Program the open-drain outputs as active-high or active-low. Programmable timing delay blocks configure each output to wait between 25s and 1600ms before deasserting. An SMBusTM/I2C-compatible serial data interface programs and communicates with the configuration EEPROM, the configuration registers, and the internal 4kb user EEPROM of the MAX6874/MAX6875. The MAX6874/MAX6875 are available in a 7mm x 7mm x 0.8mm 32-pin thin QFN package and operate over the extended temperature range (-40C to +85C).
Ordering Information
PART MAX6874 ETJ MAX6875 ETJ TEMP RANGE -40C to +85C -40C to +85C PINPACKAGE 32 Thin QFN 32 Thin QFN PKG CODE T3277-2 T3277-2
Applications
Telecommunications/Central Office Systems Networking Systems Servers/Workstations Base Stations Storage Equipment Multimicroprocessor/Voltage Systems
SMBus is a trademark of Intel Corp.
Pin Configurations, Typical Operating Circuit, and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND) IN2-IN6, ABP, SDA, SCL, A0, A1, GPI1-GPI4, MR, MARGIN, PO5-PO8 (MAX6874), PO3-PO5 (MAX6875)...................-0.3V to +6V IN1, PO1-PO4 (MAX6874), PO1-PO2 (MAX6875)...-0.3V to +14V DBP ..........................................................................-0.3V to +3V Input/Output Current (all pins)..........................................20mA Continuous Power Dissipation (TA = +70C) 32-Pin 7mm x 7mm Thin QFN (derate 33.3mW/C above +70C) .............................2667mW Operating Temperature Range ...........................-40C to +85C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN1 = +6.5V to +13.2V, VIN2-VIN6 = +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER SYMBOL VIN1 VIN3 to VIN5 VIN1P VUVLO CONDITIONS Voltage on IN1 to ensure the device is fully operational, IN3-IN6 = GND Voltage on any one of IN3-IN5 to ensure the device is fully operational, IN1 = GND Minimum voltage on IN1 to guarantee that the device is powered through IN1 Minimum voltage on one of IN3-IN5 to guarantee the device is EEPROM configured. VIN1 = +13.2V, IN2-IN6 = GND, no load Supply Current ICC Writing to configuration registers or EEPROM, no load VIN1 (50mV increments) VIN1 (25mV increments) Threshold Range VTH VIN2 (50mV increments) VIN2 (25mV increments) VIN3-VIN6 (20mV increments) VIN3-VIN6 (10mV increments) TA = +25C Threshold Accuracy Threshold Hysteresis Reset Threshold Temperature Coefficient Threshold-Voltage Differential Nonlinearity VTH-HYST VTH/C VTH DNL -1 IN1-IN6, VIN_ falling TA = -40C to +85C 2.5 1.250 2.50 1.250 1.0 0.50 -1.0 -1.5 0.3 10 +1 1.2 1.3 MIN 4.0 2.7 TYP MAX 13.2 V 5.5 6.5 2.5 1.5 2 13.2 7.625 5.5 3.05 5.5 3.05 +1.0 +1.5 % % VTH ppm/ C LSB V V V mA mA UNITS
Operating Voltage Range (Note 3)
IN1 Supply Voltage (Note 3) Undervoltage Lockout
2
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = +6.5V to +13.2V, VIN2-VIN6 = +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER IN1 Input Leakage Current IN2 Input Impedance IN3-IN6 Input Impedance Power-Up Delay IN_ to PO_ Delay SYMBOL ILIN1 RIN2 RIN3 to RIN6 tPU tDPO VIN1 > 6.5V VABP VUVLO VIN_ falling or rising, 100mV overdrive 000 001 010 PO_ Timeout Period tRP Register contents (Table 16) 011 100 101 110 111 PO1-PO4 (MAX6874), PO1-PO2 (MAX6875) Output Low (Note 3) PO5-PO8 (MAX6874), PO3-PO5 (MAX6875) Output Low (Note 3) PO1-PO8 Output Initial Pulldown Current PO1-PO8 Output Open-Drain Leakage Current VOL VOL IPD ILKG VABP +2.5V, ISINK = 500A VABP +4.0V, ISINK = 2mA VABP +2.5V, ISINK = 1mA VABP +4.0V, ISINK = 4mA VABP VUVLO, VPO_ = 0.8V Output high impedance -1 10 1.406 5.625 22.5 45 180 360 1440 25 25 1.5625 6.25 25 50 200 400 1600 1.719 6.875 27.5 55 220 440 1760 0.3 0.4 0.3 0.4 40 +1 V V A A ms CONDITIONS For VIN1 < the highest of VIN3-VIN5 160 70 MIN TYP 100 230 100 MAX 140 320 145 3.5 UNITS A k k ms s s
MAX6874/MAX6875
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3
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
ELECTRICAL CHARACTERISTICS (continued)
(VIN1 = +6.5V to +13.2V, VIN2-VIN6 = +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER MR, MARGIN, GPI_ Input Voltage MR Input Pulse Width MR Glitch Rejection MR to PO_ Delay MR to VDBP Pullup Current MARGIN to VDBP Pullup Current GPI_ to PO_ Delay GPI_ Pulldown Current Watchdog Input Pulse Width tDMR IMR IMARGIN tDGPI_ IGPI_ tWDI VGPI_ = +0.8V GPI_ configured as a watchdog input 000 001 010 Watchdog Timeout Period tWD Register Contents (Table 19) 011 100 101 110 111 SERIAL INTERFACE LOGIC (SDA, SCL, A0, A1) Logic-Input Low Voltage Logic-Input High Voltage Input Leakage Current Output Voltage Low Input/Output Capacitance VIL VIH ILKG VOL CI/O ISINK = 3mA 10 2.0 -1 +1 0.4 0.8 V V A V pF 5 50 5.625 22.5 90 360 1.44 5.76 23.04 92.16 6.25 25 100 400 1.6 6.4 25.6 102.4 6.875 27.5 110 440 1.76 7.04 28.16 112.64 s ms V MR = +1.4V V MARGIN = +1.4V 5 5 SYMBOL VIL VIH tMR 1.4 1 100 2 10 10 200 10 15 15 15 CONDITIONS MIN TYP MAX 0.8 UNITS V s ns s A A ns A ns
4
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
TIMING CHARACTERISTICS
(IN1 = GND, VIN2-VIN6 = +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Notes 1, 2)
PARAMETER TIMING CHARACTERISTICS (Figure 2) Serial Clock Frequency Clock Low Period Clock High Period Bus-Free Time START Setup Time START Hold Time STOP Setup Time Data-In Setup Time Data-In Hold Time Receive SCL/SDA Minimum Rise Time Receive SCL/SDA Maximum Rise Time Receive SCL/SDA Minimum Fall Time Receive SCL/SDA Maximum Fall Time Transmit SDA Fall Time Pulse Width of Spike Suppressed EEPROM Byte Write Cycle Time fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT tR tR tF tF tF tSP tWR (Note 4) (Note 4) (Note 4) (Note 4) CBUS = 400pF (Note 5) (Note 6) 20 + 0.1 x CBUS 50 11 1.3 0.6 1.3 0.6 0.6 0.6 100 0 20 + 0.1 x CBUS 300 20 + 0.1 x CBUS 300 300 900 400 kHz s s s s s s ns ns ns ns ns ns ns ns ms SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX6874/MAX6875
Note 1: Specifications guaranteed for the stated global conditions. The device also meets the parameters specified when 0 < VIN1 < +6.5V, and at least one of VIN3-VIN6 is between +2.7V and +5.5V, while the remaining V IN3-VIN6 are between 0 and +5.5V. Note 2: Device may be supplied from any one of IN_, except IN2 and IN6. Note 3: The internal supply voltage, measured at ABP, equals the maximum of IN3-IN5 if VIN1 = 0, or equals +5.4V if VIN1 > +6.5V. For +4V < VIN1 < +6.5V and VIN3-VIN5 > +2.7V, the input that powers the device cannot be determined. Note 4: CBUS = total capacitance of one bus line in pF. Rise and fall times are measured between 0.1 x VBUS and 0.9 x VBUS. Note 5: Input filters on SDA, SCL, A0, and A1 suppress noise spikes < 50ns. Note 6: An additional cycle is required when writing to configuration memory for the first time.
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5
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Typical Operating Characteristics
(VIN1 = +6.5V to +13.2V, VIN2-VIN6 = +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (IN1)
MAX6874/75 toc01
SUPPLY CURRENT vs. SUPPLY VOLTAGE (IN3 TO IN5)
MAX6874/75 toc02
NORMALIZED PO_ TIMEOUT PERIOD vs. TEMPERATURE
1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 -40 -15 10 35 60 85
MAX6874/753 toc03
1.5 1.4 SUPPLY CURRENT (mA) 1.3 1.2 1.1 1.0 0.9 0.8 6.5 7.5 8.5 9.5 10.5 11.5 12.5 TA = -40C TA = +25C TA = +85C
1.5 1.4 SUPPLY CURRENT (mA) 1.3 1.2 1.1 1.0 0.9 0.8 TA = -40C TA = +25C TA = +85C
1.04 NORMALIZED PO_ TIMEOUT PERIOD
13.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
IN_ TO PO_ PROPAGATION DELAY vs. TEMPERATURE
IN_ TO PO_ OUTPUT PROPAGATION DELAY (s)
MAX6874/75 toc04
NORMALIZED WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE
MAX6874/75 toc05
NORMALIZED IN_ THRESHOLD vs. TEMPERATURE
1.008 NORMALIZED IN_ THRESHOLD 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 0.990 IN3 THRESHOLD = 1V, 20mV/STEP RANGE
MAX6874/75 toc06
28 26 24 22 20 18 16 14 12 10 -40
100mV OVERDRIVE
NORMALIZED WATCHDOG TIMEOUT PERIOD
30
1.020 1.015 1.010 1.005 1.000 0.995 0.990 0.985 0.980 -40 -15 10 35 60
1.010
-15
10
35
60
85
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TEMPERATURE (C)
6
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Typical Operating Characteristics (continued)
(VIN1 = +6.5V to +13.2V, VIN2-VIN6 = +2.7V to +5.5V, GPI_ = GND, MARGIN = MR = DBP, TA = +25C, unless otherwise noted.)
MAXIMUM IN_ TRANSIENT DURATION vs. IN_ THRESHOLD OVERDRIVE
130 120 110 100 90 80 70 60 50 40 30 20 10 0 1 10
MAX6874/75 toc07
OUTPUT VOLTAGE LOW vs. SINK CURRENT
400 350 300 VOL (mV) 250 200 150 100 50 0 PO5-PO8 (MAX6874) PO3-PO5 (MAX6875) PO1-PO4 (MAX6874) PO1-PO2 (MAX6875)
MAX6874/75 toc08
450
MAXIMUM IN_ TRANSIENT DURATION (s)
PO_ ASSERTION OCCURS ABOVE THIS LINE
100
1000
IN_ THRESHOLD OVERDRIVE (mV)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ISINK (mA)
MR TO PO_ PROPAGATION DELAY vs. TEMPERATURE
MAX6874/75 toc09
MAXIMUM MR TRANSIENT DURATION vs. MR THRESHOLD OVERDRIVE
MAXIMUM MR TRANSIENT DURATION (s) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1 10 100 1000 MR THRESHOLD OVERDRIVE (mV) PO_ ASSERTION OCCURS ABOVE THIS LINE
MAX6874/75 toc10
1.90 MR TO PO_ PROPAGATION DELAY (s) 1.85 1.80 1.75 1.70 1.65 1.60 1.55 1.50 -40 -15 10 35 60
85
TEMPERATURE (C)
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7
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Pin Description
PIN MAX6874 1 MAX6875 3 NAME FUNCTION Programmable Output 2. Configurable active-high or active-low open-drain output. PO2 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO2 assumes its programmed conditional output state when ABP exceeds UVLO. Programmable Output 3. Configurable active-high or active-low open-drain output. PO3 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO3 assumes its programmed conditional output state when ABP exceeds UVLO. Programmable Output 4. Configurable active-high or active-low open-drain output. PO4 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO4 assumes its programmed conditional output state when ABP exceeds UVLO. Ground Programmable Output 5. Configurable active-high or active-low open-drain output. PO5 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO5 assumes its programmed conditional output state when ABP exceeds UVLO. Programmable Output 6. Configurable active-high or active-low open-drain output. PO6 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO6 assumes its programmed conditional output state when ABP exceeds UVLO. Programmable Output 7. Configurable active-high or active-low open-drain output. PO7 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO7 assumes its programmed conditional output state when ABP exceeds UVLO. Programmable Output 8. Configurable active-high or active-low open-drain output. PO8 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO8 assumes its programmed conditional output state when ABP exceeds UVLO.
PO2
2
5
PO3
3 4 5
6 4 7
PO4 GND PO5
6
--
PO6
7
--
PO7
8
--
PO8
9, 10, 23, 24
1, 8, 9,10, 16, 17, 23-26, 32
N.C.
No Connection. Not internally connected.
11
11
MARGIN
Margin Input. Drive MARGIN low to hold PO_ in their existing states. Leave MARGIN unconnected or connect to DBP if unused. MARGIN overrides MR if both assert at the same time. MARGIN is internally pulled up to DBP through a 10A current source. Manual Reset Input. MR to either assert PO_ into a programmed state or to have no effect on PO_ when driving MR low (see Table 6). Leave MR unconnected or connect to DBP if unused. MR is internally pulled up to DBP through a 10A current source. Serial Data Input/Output (Open-Drain). SDA requires an external pullup resistor. Serial Clock Input. SCL requires an external pullup resistor. Address Input 0. Address inputs allow up to four MAX6874 or two MAX6875 connections on one common bus. Connect A0 to GND or to the serial interface power supply. Address Input 1 (MAX6874 only). Address inputs allow up to four MAX6874 connections on one common bus. Connect A1 to GND or to the serial interface power supply.
12 13 14 15 16
12 13 14 15 --
MR SDA SCL A0 A1
8
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Pin Description (continued)
PIN MAX6874 17 18 19 20 MAX6875 -- 18 19 20 NAME GPI4 GPI3 GPI2 GPI1 FUNCTION General-Purpose Logic Input 4 (MAX6874 Only). An internal 10A current source pulls GPI4 to GND. Configure GPI4 to control watchdog timer functions or the programmable outputs. General-Purpose Logic Input 3. An internal 10A current source pulls GPI3 to GND. Configure GPI3 to control watchdog timer functions or the programmable outputs. General-Purpose Logic Input 2. An internal 10A current source pulls GPI2 to GND. Configure GPI2 to control watchdog timer functions or the programmable outputs. General-Purpose Logic Input 1. An internal 10A current source pulls GPI1 to GND. Configure GPI1 to control watchdog timer functions or the programmable outputs. Internal Power-Supply Output. Bypass ABP to GND with a 1F ceramic capacitor. ABP powers the internal circuitry of the MAX6874/MAX6875. Do not use ABP to supply power to external circuitry. Internal Digital Power-Supply Output. Bypass DBP to GND with a 1F ceramic capacitor. DBP supplies power to the EEPROM memory and the internal logic circuitry. Do not use DBP to supply power to external circuitry. Voltage Input 6. Configure IN6 to detect voltage thresholds between +1V and +5.5V in 20mV increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN6 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 5. Configure IN5 to detect voltage thresholds between +1V and +5.5V in 20mV increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN5 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 4. Configure IN4 to detect voltage thresholds between +1V and +5.5V in 20mV increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN4 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 3. Configure IN3 to detect voltage thresholds between +1V and +5.5V in 20mV increments, or +0.5V to +3.05V in 10mV increments. For improved noise immunity, bypass IN3 to GND with a 0.1F capacitor installed as close to the device as possible. Voltage Input 2. Configure IN2 to detect voltage thresholds from +2.5V to +5.5V in 50mV increments or +1.25V to +3.05V in 25mV increments. For improved noise immunity, bypass IN2 to GND with a 0.1F capacitor installed as close to the device as possible. High-Voltage Input 1. Configure IN1 to detect voltage thresholds from +2.5V to +13.2V in 50mV increments or +1.25V to +7.6V in 25mV increments. For improved noise immunity, bypass IN1 to GND with a 0.1F capacitor installed as close to the device as possible. Internal Connection. Leave unconnected. Programmable Output 1. Configurable active-high or active-low open-drain output. PO1 pulls low with a 10A internal current sink for +1V < VABP < VUVLO. PO1 assumes its programmed conditional output state when ABP exceeds UVLO. Exposed Paddle. Exposed paddle is internally connected to GND.
MAX6874/MAX6875
21
21
ABP
22
22
DBP
25
--
IN6
26
--
IN5
27
27
IN4
28
28
IN3
29
29
IN2
30 31 32 --
30 31 2 --
IN1 I.C. PO1 EP
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9
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Detailed Description
The MAX6874/MAX6875 EEPROM-configurable, multivoltage supply sequencers/supervisors monitor several voltage detector inputs and general-purpose logic inputs, and feature programmable outputs for highly configurable power-supply sequencing applications. The MAX6874 features six voltage detector inputs, four general-purpose logic inputs, and eight programmable outputs, while the MAX6875 features four voltage detector inputs, three general-purpose logic inputs, and five programmable outputs. Manual reset and margin disable inputs simplify board-level testing during the manufacturing process. The MAX6874/MAX6875 feature an accurate internal 1.25V reference. All voltage detectors provide configurable thresholds for undervoltage detection. One high-voltage input (IN1) provides detector threshold voltages from +1.25V to +7.625V in 25mV increments or +2.5V to +13.2V in 50mV increments. A positive input (IN2) provides detector threshold voltages from +1.25V to +3.05V in 25mV increments or +2.5V to +5.5V in 50mV increments. Positive inputs (IN3-IN6) provide detector threshold voltages from +0.5V to +3.05V in 10mV increments or +1.0V to +5.5V in 20mV increments. The host controller communicates with the MAX6874/ MAX6875's internal 4kb user EEPROM, configuration EEPROM, and configuration registers through an SMBus/I2C-compatible serial interface (see Figure 1). Program the open-drain outputs as active-high or activelow. Program each output to assert on any voltage detector input, general-purpose logic input, watchdog timer, manual reset, or other output stages. Programmable timing delay blocks configure each output to wait between 25s and 1600ms before de-asserting. The MAX6874/MAX6875 feature a watchdog timer, adding flexibility. Program the watchdog timer to assert one or more programmable outputs. Program the watchdog timer to clear on a combination of one GPI_ input and one programmable output, one of the GPI_ inputs only, or one of the programmable outputs only. The initial and normal watchdog timeout periods are independently programmable from 6.25ms to 102.4s. A virtual diode-ORing scheme selects the input that powers the MAX6874/MAX6875. The MAX6874/MAX6875 derive power from IN1 if VIN1 > +6.5V or from the highest voltage on IN3-IN5 if VIN1 < +2.7V. The power source cannot be determined if +4V < VIN1 < +6.5V and one of VIN3 through VIN5 > +2.7V. The programmable outputs maintain the correct programmed logic state for V ABP > V UVLO . One of IN3 through IN5 must be greater than +2.7V or IN1 must be greater than +4V for device operation.
IN_
COMPARATORS
LOGIC NETWORK FOR PO_
OUTPUT STAGES
PO_
GPI_, MR, MARGIN
WATCHDOG TIMER
GPI_
SDA, SCL
SERIAL INTERFACE
REGISTER BANK EEPROM (USER AND CONFIG) CONTROLLER
ANALOG BLOCK DIGITAL BLOCK
Figure 1. Top-Level Block Diagram 10 ______________________________________________________________________________________
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Functional Diagram
GPI2 GPI3 GPI4 (N.C.) MARGIN MR
MAX6874/MAX6875
IN1
IN_ DETECTOR
GPI1
PO1 PO_ OUTPUT
1.25V VREF IN2 IN3 IN4 IN5 (N.C.) IN6 (N.C.) IN2 DETECTOR IN3 DETECTOR IN4 DETECTOR IN5 DETECTOR IN6 DETECTOR PROGRAMMABLE ARRAY
TIMING BLOCK 1 TIMING BLOCK 2 TIMING BLOCK 3 TIMING BLOCK 4 TIMING BLOCK 5 TIMING BLOCK 6 TIMING BLOCK 7 5.4V LDO (VIRTUAL DIODES) TIMING BLOCK 8 PO2 OUTPUT PO3 OUTPUT PO4 OUTPUT PO5 OUTPUT PO6 OUTPUT PO7 OUTPUT PO8 OUTPUT PO2 PO3 PO4 PO5 PO6 (N.C.) PO7 (N.C.) PO8 (N.C.)
MAIN OSCILLATOR
2.55V LDO DBP 1F ABP 1F
MAX6874 MAX6875
EEPROM CHARGE PUMP CONFIG CONFIG REGISTERS EEPROM USER EEPROM
SDA SERIAL INTERFACE SCL A0 A1 (N.C.)
GND
( ) ARE FOR MAX6875 ONLY.
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11
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Powering the MAX6874/MAX6875
The MAX6874/MAX6875 derive power from the positive voltage-detector inputs: IN1 or IN3-IN5. A virtual diodeORing scheme selects the positive input that supplies power to the device (see the Functional Diagram). IN1 must be at least +4V or one of IN3-IN5 (MAX6874)/ IN3-IN4 (MAX6875) must be at least +2.7V to ensure device operation. An internal LDO regulates IN1 down to +5.4V. The highest input voltage on IN3-IN5 (MAX6874)/ IN3-IN4 (MAX6875) supplies power to the device, unless VIN1 +6.5V, in which case IN1 supplies power to the device. For +4V < VIN1 < +6.5V and one of VIN3 through VIN5 > +2.7V, the input power source cannot be determined due to the dropout voltage of the LDO. Internal hysteresis ensures that the supply input that initially powered the device continues to power the device when multiple input voltages are within 50mV of each other. ABP powers the analog circuitry; bypass ABP to GND with a 1F ceramic capacitor installed as close to the device as possible. The internal supply voltage, measured at ABP, equals the maximum of IN3-IN5 (MAX6874)/IN3-IN4 (MAX6875) if VIN1 = 0, or equals +5.4V when VIN1 > +6.5V. Do not use ABP to provide power to external circuitry. The MAX6874/MAX6875 also generate a digital supply voltage (DBP) for the internal logic circuitry and the EEPROM; bypass DBP to GND with a 1F ceramic capacitor installed as close to the device as possible. The nominal DBP output voltage is +2.55V. Do not use DBP to provide power to external circuitry.
Inputs
The MAX6874/MAX6875 contain multiple logic and voltage-detector inputs. Table 1 summarizes these various inputs. Set the threshold voltages for each voltage-detector input with registers 00h-05h. Each threshold voltage is an undervoltage threshold. Set the threshold range for each voltage detector with register 0Dh.
Table 1. Programmable Features
FEATURE High-Voltage Input (IN1) * * * * * * * * * DESCRIPTION Undervoltage threshold +2.5V to +13.2V threshold in 50mV increments +1.25V to +7.625V threshold in 25mV increments Undervoltage threshold +2.5V to +5.5V threshold in 50mV increments +1.25V to +3.05V threshold in 25mV increments Undervoltage threshold +1V to +5.5V threshold in 20mV increments +0.5V to +3.05V threshold in 10mV increments Active high or active low Open-drain output Dependent on MR, MARGIN, IN_, GPI1-GPI4 , WD, and/or PO_ Programmable timeout periods of 25s, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms, or 1.6s
Voltage Input (IN2)
Voltage Input IN3-IN6 (MAX6874), IN3-IN4 (MAX6875)
* Programmable Outputs * PO1-PO8 (MAX6874), * PO1-PO5 (MAX6875) * General-Purpose Logic Inputs, * GPI1-GPI4 (MAX6874), * GPI1-GPI3 (MAX6875) * Watchdog Timer * * *
Active-high or active-low logic levels Configure GPI_ as inputs to watchdog timers or programmable output stages Clear dependent on any combination of one GPI_ input and one programmable output, a GPI_ input only, or a programmable output only Initial watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s Normal watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s Watchdog enable/disable
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Table 1. Programmable Features (continued)
FEATURE Manual Reset Input (MR) Write Disable Configuration Lock * * * * * DESCRIPTION Forces PO_ into the active output state when MR = GND PO_ deassert after MR releases high and the PO_ timeout period expires PO_ cannot be a function of MR only Locks user EEPROM based on PO_ Locks configuration EEPROM
MAX6874/MAX6875
High-Voltage Input (IN1) IN1 offers threshold voltages of +2.5V to +13.2V in 50mV increments, or +1.25V to +7.625V in 25mV increments. Use the following equations to set the threshold voltages for IN1: V - 2.5V x = TH for + 2.5V to + 13.2V range 0.05V V - 1.25V x = TH for + 1.25V to + 7.625V range 0.025V where VTH is the desired threshold voltage and x is the decimal code for the desired threshold (Table 2). For the +2.5V to +13.2V range, x must equal 214 or less, otherwise the threshold exceeds the maximum operating voltage of IN1. IN2 IN2 offers thresholds from +2.5V to +5.5V in 50mV increments, or +1.25V to +3.05V in 25mV increments. Use the following equations to set the threshold voltages for IN2: V - 2.5V x = TH for + 2.5V to + 5.5V range 0.05V
V - 1.25V x = TH for + 1.25V to + 3.05V range 0.025V where VTH is the desired threshold voltage and x is the decimal code for the desired threshold (Table 3). For the +2.5V to +5.5V range, x must equal 60 or less, otherwise the threshold exceeds the maximum operating voltage of IN2. For the +1V to +3.05V range, x must equal 72 or less. IN3-IN6 IN3-IN6 offer positive voltage detectors monitor voltages from +1V to +5.5V in 20mV increments, or +0.5V to +3.05V in 10mV increments. Use the following equations to set the threshold voltages for IN_: V - 1V x = TH for + 1V to + 5.5V range 0.02V V - 0.5V x = TH for + 0.5V to + 3.05V range 0.01V where VTH is the desired threshold voltage and x is the decimal code for the desired threshold (Table 4). For the +1V to +5.5V range, x must equal 225 or less, otherwise the threshold exceeds the maximum operating voltage of IN3-IN6.
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 2. IN1 Threshold Settings
REGISTER ADDRESS EEPROM MEMORY ADDRESS 8000h 800Dh BIT RANGE DESCRIPTION
00h 0Dh
[7:0] [0]
IN1 detector threshold (V1) (see equations in the High-Voltage Input (IN1) section). IN1 range selection: 0 = 2.5V to 13.2V range in 50mV increments. 1 = 1.25V to 7.625V range in 25mV increments.
Table 3. IN2 Threshold Settings
REGISTER ADDRESS EEPROM MEMORY ADDRESS 8001h BIT RANGE DESCRIPTION
01h
[7:0]
IN2 detector threshold (V2) (see equations in the IN2 section). IN2 range selection: 00 = Not used. 01 = Not used. 10 = +2.5V to +5.5V range in 50mV increments. 11 = +1.25V to +3.05V range in 25mV increments.
0Dh
800Dh
[7:6]
Table 4. IN3-IN6 Threshold Settings
REGISTER ADDRESS 02h 03h 04h 05h EEPROM MEMORY ADDRESS 8002h 8003h 8004h 8005h BIT RANGE [7:0] [7:0] [7:0] [7:0] [1] [2] 0Dh 800Dh [3] [4] [5] DESCRIPTION IN3 detector threshold (V3) (see equations in the IN3-IN6 section). IN4 detector threshold (V4) (see equations in the IN3-IN6 section). IN5 (MAX6874 only) detector threshold (V5) (see equations in the IN3-IN6 section). IN6 (MAX6874 only) detector threshold (V6) (see equations in the IN3-IN6 section). IN3 range selection: 0 = +1V to +5.5V range in 20mV increments. 1 = +0.5V to +3.05V range in 10mV increments. IN4 range selection: 0 = +1V to +5.5V range in 20mV increments. 1 = +0.5V to +3.05V range in 10mV increments. IN5 (MAX6874 only) range selection: 0 = +1V to +5.5V range in 20mV increments. 1 = +0.5V to +3.05V range in 10mV increments. IN6 (MAX6874 only) range selection: 0 = +1V to +5.5V range in 20mV increments. 1 = +0.5V to +3.05V range in 10mV increments. Not used.
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GPI1-GPI4 (MAX6874)/GPI1-GPI3 (MAX6875) The GPI1-GPI4 programmable logic inputs control power-supply sequencing (programmable outputs), reset/interrupt signaling, and watchdog functions (see the Configuring the Watchdog Timer (Registers 3Ch-3Dh) section). Configure GPI1-GPI4 for active-low or active-high logic (Table 5). GPI1-GPI4 internally pull down to GND through a 10A current sink.
MR The manual reset (MR) input initiates a reset condition. Register 40h determines the programmable outputs that assert while MR is low (Table 6). All affected programmable outputs remain asserted (see the Programmable Outputs section) for their PO_ timeout periods after MR releases high. An internal 10A current source pulls MR to DBP. Leave MR unconnected or connect to DBP if unused. A programmable output cannot depend solely on MR.
MARGIN MARGIN allows system-level testing while power supplies exceed the normal ranges. Drive MARGIN low to hold the programmable outputs in their state while system-level testing occurs. Leave MARGIN unconnected or connect to DBP if unused. An internal 10A current source pulls MARGIN to DBP. The state of each programmable output does not change while MARGIN = GND. MARGIN overrides MR if both assert at the same time.
MAX6874/MAX6875
Programmable Outputs
The MAX6874 features eight programmable outputs while the MAX6875 features five programmable outputs. Program the open-drain outputs as active-high or active-low. During power-up, the programmable outputs pull to GND with an internal 10A current sink for 1V < VABP < VUVLO. The programmable outputs remain in their active states until their respective timeout periods (PO_) expire and all of the programmed conditions are met for each output. Any output programmed to depend
Table 5. GPI1-GPI4 Active Logic States
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] 3Bh 803Bh [1] [2] [3] GPI1. 0 = active low. 1 = active high. GPI2. 0 = active low. 1 = active high. GPI3. 0 = active low. 1 = active high. GPI4 (MAX6874 only). 0 = active low. 1 = active high. DESCRIPTION
Table 6. Programmable Output Behavior and MR
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] [3] 40h 8040h [4] [5] [6] [7] DESCRIPTION PO1 (MAX6874 only). 0 = PO1 independent of MR. 1 = PO1 asserts when MR = low. PO2 (MAX6874 only). 0 = PO2 independent of MR. 1 = PO2 asserts when MR = low. PO3 (MAX6874)/PO1 (MAX6875). 0 = PO3/PO1 independent of MR. 1 = PO3/PO1 asserts when MR = low. PO4 (MAX6874)/PO2 (MAX6875). 0 = PO4/PO2 independent of MR. 1 = PO4/PO2 asserts when MR = low. PO5 (MAX6874)/PO3 (MAX6875). 0 = PO5/PO3 independent of MR. 1 = PO5/PO3 asserts when MR = low. PO6 (MAX6874)/PO4 (MAX6875). 0 = PO6/PO4 independent of MR. 1 = PO6/PO4 asserts when MR = low. PO7 (MAX6874)/PO5 (MAX6875). 0 = PO7/PO5 independent of MR. 1 = PO7/PO5 asserts when MR = low. PO8 (MAX6874 only). 0 = PO8 independent of MR. 1 = PO8 asserts when MR = low.
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 7. PO1 (MAX6874 Only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 0Eh 800Eh [3] [4] [5] [6] [7] [5:0] 0Fh 800Fh [6] [7] [0] [1] [2] 10h 8010h [3] [4] [5] [6] [7] 11h 40h 8011h 8040h [0] [0] OUTPUT ASSERTION CONDITIONS 1 = PO1 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO1 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO1 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO1 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO1 assertion depends on IN5 undervoltage threshold (Table 4). 1 = PO1 assertion depends on IN6 undervoltage threshold (Table 4). 1 = PO1 assertion depends on watchdog (Tables 19 and 20). Must be set to 0. Must be set to 0. 1 = PO1 assertion depends on GPI1 (Table 5). 1 = PO1 assertion depends on GPI2 (Table 5). 1 = PO1 assertion depends on GPI3 (Table 5). 1 = PO1 assertion depends on GPI4 (Table 5). 1 = PO1 assertion depends on PO2 (Table 8). 1 = PO1 assertion depends on PO3 (Table 9). 1 = PO1 assertion depends on PO4 (Table 10). 1 = PO1 assertion depends on PO5 (Table 11). 1 = PO1 assertion depends on PO6 (Table 12). 1 = PO1 assertion depends on PO7 (Table 13). 1 = PO1 assertion depends on PO8 (Table 14). 1 = PO1 asserts when MR = low (Table 6).
on no condition always remains in its active state (Table 19). An output configured as active-high is considered asserted when that output is logic high. No output can depend solely on MR. The voltage monitors generate fault signals (logical 0) to the MAX6874/MAX6875s' logic array when an input voltage is below the programmed undervoltage threshold. Registers 0Eh through 3Ah and 40h configure each of the programmable outputs. Programmable timing blocks set the PO_ timeout period from 25s to 1600ms for each programmable output. See register 3Ah (Table 15) to set the active state (active-high or active-low) for each programmable output and Table 16 for timeout periods for each output.
For example, PO3 (MAX6874--Table 9) may depend on the IN1 undervoltage threshold, and the states of GPI1, PO1, and PO2. Write a one to R16h[0], R17h[6], and R18h[3:2] to configure the output as indicated. IN1 must be above the undervoltage threshold (Table 2), GPI1 must be inactive (Table 5), and PO1 (Tables 7 and 15) and PO2 (Table 9) must be in their deasserted states for the output to deassert. Table 7 only applies to PO1 of the MAX6874. Write a 0 to a bit to make the PO1 output independent of the respective signal (IN1-IN6 thresholds, WD, GPI1-GPI4, MR, or other programmable outputs).
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Table 8. PO2 (MAX6874 Only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 12h 8012h [3] [4] [5] [6] [7] [5:0] 13h 8013h [6] [7] [0] [1] [2] 14h 8014h [3] [4] [5] [6] [7] 15h 40h 8015h 8040h [0] [1] OUTPUT ASSERTION CONDITIONS 1 = PO2 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO2 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO2 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO2 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO2 assertion depends on IN5 undervoltage threshold (Table 4). 1 = PO2 assertion depends on IN6 undervoltage threshold (Table 4). 1 = PO2 assertion depends on watchdog (Tables 18 and 19). Must be set to 0. Must be set to 0. 1 = PO2 assertion depends on GPI1 (Table 5). 1 = PO2 assertion depends on GPI2 (Table 5). 1 = PO2 assertion depends on GPI3 (Table 5). 1 = PO2 assertion depends on GPI4 (Table 5). 1 = PO2 assertion depends on PO1 (Table 7). 1 = PO2 assertion depends on PO3 (Table 9). 1 = PO2 assertion depends on PO4 (Table 10). 1 = PO2 assertion depends on PO5 (Table 11). 1 = PO2 assertion depends on PO6 (Table 12). 1 = PO2 assertion depends on PO7 (Table 13). 1 = PO2 assertion depends on PO8 (Table 14). 1 = PO2 asserts when MR = low (Table 6).
MAX6874/MAX6875
Table 8 only applies to PO2 of the MAX6874. Write a 0 to a bit to make the PO2 output independent of the
respective signal (IN1-IN6 thresholds, WD, GPI1-GPI4, MR, or other programmable outputs).
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 9. PO3 (MAX6874)/PO1 (MAX6875) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 16h 8016h [4] [5] [6] [7] [5:0] 17h 8017h [6] [7] [0] [1] [2] 18h 8018h [3] [4] [5] [6] [7] 1Ch 40h 801Ch 8040h [1:0] [2] OUTPUT ASSERTION CONDITIONS 1 = PO3/PO1 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO3/PO1 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO3/PO1 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO3/PO1 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO3 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO3 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO3/PO1 assertion depends on watchdog (Tables 18 and 19). Must be set to 0. Must be set to 0. 1 = PO3/PO1 assertion depends on GPI1 (Table 5). 1 = PO3/PO1 assertion depends on GPI2 (Table 5). 1 = PO3/PO1 assertion depends on GPI3 (Table 5). 1 = PO3/PO1 assertion depends on GPI4 (Table 5). 1 = PO3 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875. 1 = PO3 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875. 1 = PO3/PO1 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10). 1 = PO3/PO1 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11). 1 = PO3/PO1 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12). 1 = PO3/PO1 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13). 1 = PO3 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875. 1 = PO3/PO1 asserts when MR = low (Table 6).
Table 9 only applies to PO3 of the MAX6874 and PO1 of the MAX6875. Write a 0 to a bit to make the PO3/PO1 output independent of the respective signal (IN_
thresholds, WD, GPI1-GPI4, MR, or other programmable outputs).
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Table 10. PO4 (MAX6874)/PO2 (MAX6875) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 1Dh 801Dh [4] [5] [6] [7] [5:0] 1Eh 801Eh [6] [7] [0] [1] [2] 1Fh 801Fh [3] [4] [5] [6] [7] 23h 40h 8023h 8040h [0] [3] OUTPUT ASSERTION CONDITIONS 1 = PO4/PO2 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO4/PO2 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO4/PO2 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO4/PO2 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO4 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO4 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO4/PO2 assertion depends on watchdog (Tables 18 and 19). Must be set to 0. Must be set to 0. 1 = PO4/PO2 assertion depends on GPI1 (Table 5). 1 = PO4/PO2 assertion depends on GPI2 (Table 5). 1 = PO4/PO2 assertion depends on GPI3 (Table 5). 1 = PO4/PO2 assertion depends on GPI4 (Table 5). 1 = PO4 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875. 1 = PO4 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875. 1 = PO4/PO2 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9). 1 = PO4/PO2 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11). 1 = PO4/PO2 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12). 1 = PO4/PO2 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13). 1 = PO4 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875. 1 = PO4/PO2 asserts when MR = low (Table 6).
MAX6874/MAX6875
Table 10 only applies to PO4 of the MAX6874 and PO2 of the MAX6875. Write a 0 to a bit to make the PO4/PO2 output independent of the respective signal (IN_
thresholds, WD, GPI1-GPI4, MR, or other programmable outputs).
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 11. PO5 (MAX6874)/PO3 (MAX6875) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 24h 8024h [4] [5] [6] [7] [5:0] 25h 8025h [6] [7] [0] [1] [2] 26h 8026h [3] [4] [5] [6] [7] 2Ah 40h 802Ah 8040h [0] [4] OUTPUT ASSERTION CONDITIONS 1 = PO5/PO3 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO5/PO3 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO5/PO3 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO5/PO3 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO5 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO5 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO5/PO3 assertion depends on watchdog (Tables 18 and 19). Must be set to 0. Must be set to 0. 1 = PO5/PO3 assertion depends on GPI1 (Table 5). 1 = PO5/PO3 assertion depends on GPI2 (Table 5). 1 = PO5/PO3 assertion depends on GPI3 (Table 5). 1 = PO5/PO3 assertion depends on GPI4 (Table 5). 1 = PO5 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875. 1 = PO5 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875. 1 = PO5/PO3 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9). 1 = PO5/PO3 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10). 1 = PO5/PO3 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12). 1 = PO5/PO3 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13). 1 = PO5 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875. 1 = PO5/PO3 asserts when MR = low (Table 6).
Table 11 only applies to PO5 of the MAX6874 and PO3 of the MAX6875. Write a 0 to a bit to make the PO5/PO3 output independent of the respective signal (IN_
thresholds, WD, GPI1-GPI4, MR, or other programmable outputs).
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Table 12. PO6 (MAX6874)/PO4 (MAX6875) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 2Bh 802Bh [4] [5] [6] [7] [5:0] 2Ch 802Ch [6] [7] [0] [1] [2] 2Dh 802Dh [3] [4] [5] [6] [7] 31h 40h 8031h 8040h [0] [5] OUTPUT ASSERTION CONDITIONS 1 = PO6/PO4 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO6/PO4 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO6/PO4 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO6/PO4 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO6 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO6 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO6/PO4 assertion depends on watchdog (Tables 18 and 19). Must be set to 0. Must be set to 0. 1 = PO6/PO4 assertion depends on GPI1 (Table 5). 1 = PO6/PO4 assertion depends on GPI2 (Table 5). 1 = PO6/PO4 assertion depends on GPI3 (Table 5). 1 = PO6/PO4 assertion depends on GPI4 (Table 5). 1 = PO6 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875. 1 = PO6 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875. 1 = PO6/PO4 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9). 1 = PO6/PO4 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10). 1 = PO6/PO4 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11). 1 = PO6/PO4 assertion depends on PO7 (MAX6874)/PO5 (MAX6875) (Table 13). 1 = PO6 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875. 1 = PO6/PO4 asserts when MR = low (Table 6).
MAX6874/MAX6875
Table 12 only applies to PO6 of the MAX6874 and PO4 of the MAX6875. Write a 0 to a bit to make the PO6/PO4 output independent of the respective signal (IN_
thresholds, WD, GPI1-GPI4, MR, or other programmable outputs).
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 13. PO7 (MAX6874)/PO5 (MAX6875) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] [3] 32h 8032h [4] [5] [6] [7] [5:0] 33h 8033h [6] [7] [0] [1] [2] 34h 8034h [3] [4] [5] [6] [7] 35h 40h 8035h 8040h [0] [6] OUTPUT ASSERTION CONDITIONS 1 = PO7/PO5 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO7/PO5 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO7/PO5 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO7/PO5 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO7 (MAX6874 only) assertion depends on IN5 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO7 (MAX6874 only) assertion depends on IN6 undervoltage threshold (Table 4). Must be set to 0 for the MAX6875. 1 = PO7/PO5 assertion depends on watchdog (Tables 18 and 19). Must be set to 0. Must be set to 0. 1 = PO7/PO5 assertion depends on GPI1 (Table 5). 1 = PO7/PO5 assertion depends on GPI2 (Table 5). 1 = PO7/PO5 assertion depends on GPI3 (Table 5). 1 = PO7/PO5 assertion depends on GPI4 (Table 5). 1 = PO7 (MAX6874 only) assertion depends on PO1 (Table 7). Must be set to 0 for the MAX6875. 1 = PO7 (MAX6874 only) assertion depends on PO2 (Table 8). Must be set to 0 for the MAX6875. 1 = PO7/PO5 assertion depends on PO3 (MAX6874)/PO1 (MAX6875) (Table 9). 1 = PO7/PO5 assertion depends on PO4 (MAX6874)/PO2 (MAX6875) (Table 10). 1 = PO7/PO5 assertion depends on PO5 (MAX6874)/PO3 (MAX6875) (Table 11). 1 = PO7/PO5 assertion depends on PO6 (MAX6874)/PO4 (MAX6875) (Table 12). 1 = PO7 (MAX6874 only) assertion depends on PO8 (Table 14). Must be set to 0 for the MAX6875. 1 = PO7 asserts when MR = low (Table 6).
Table 13 only applies to PO7 of the MAX6874 and PO5 of the MAX6875. Write a 0 to a bit to make the PO7/PO5 output independent of the respective signal (IN_
thresholds, WD, GPI1-GPI4, MR, or other programmable outputs).
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Table 14. PO8 (MAX6874 only) Output Dependency
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT [0] [1] [2] 36h 8036h [3] [4] [5] [6] [7] [5:0] 37h 8037h [6] [7] [0] [1] [2] 38h 8038h [3] [4] [5] [6] [7] 39h 40h 8039h 8040h [0] [7] OUTPUT ASSERTION CONDITIONS 1 = PO8 assertion depends on IN1 undervoltage threshold (Table 2). 1 = PO8 assertion depends on IN2 undervoltage threshold (Table 3). 1 = PO8 assertion depends on IN3 undervoltage threshold (Table 4). 1 = PO8 assertion depends on IN4 undervoltage threshold (Table 4). 1 = PO8 assertion depends on IN5 undervoltage threshold (Table 4). 1 = PO8 assertion depends on IN6 undervoltage threshold (Table 4). 1 = PO8 assertion depends on watchdog (Tables 18 and 19). Must set to 0. Must set to 0. 1 = PO8 assertion depends on GPI1 (Table 5). 1 = PO8 assertion depends on GPI2 (Table 5). 1 = PO8 assertion depends on GPI3 (Table 5). 1 = PO8 assertion depends on GPI4 (Table 5). 1 = PO8 assertion depends on PO1 (Table 7). 1 = PO8 assertion depends on PO2 (Table 8). 1 = PO8 assertion depends on PO3 (Table 9). 1 = PO8 assertion depends on PO4 (Table 10). 1 = PO8 assertion depends on PO5 (Table 11). 1 = PO8 assertion depends on PO6 (Table 12). 1 = PO8 assertion depends on PO7 (Table 13). 1 = PO8 asserts when MR = low (Table 6).
MAX6874/MAX6875
Table 14 only applies to PO8 of the MAX6874. Write a 0 to a bit to make the PO8 output independent of the respective signal (IN1-IN6 thresholds, WD, GPI1-GPI4, MR, or other programmable outputs). Output Stage Configurations Independently program each programmable output as active-high or active-low (Table 15). All programmable outputs of the MAX6874/MAX6875 are open-drain only. See Table 16 to set the timeout period for each output. Open-Drain Output Configuration Connect an external pullup resistor from the programmable output to an external voltage when configured as an open-drain output. PO1-PO4 (PO1 and PO2 for the
MAX6875) may be pulled up to +13.2V. PO5-PO8 (PO3-PO5 for the MAX6875) may be pulled up to a voltage less than or equal to ABP. Choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consumption. The open-drain output configuration allows wire-ORed connections, and provides flexibility in setting the pullup current.
Configuring the MAX6874/MAX6875
The MAX6874/MAX6875 factory-default configuration sets all EEPROM registers to 00h except register 3Ah, which is set to FFh. This configuration sets all of the programmable outputs as active-high (putting all outputs into high-impedance states until the device is reconfig-
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23
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 15. Programmable Output Active States
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] 3Ah 803Ah [3] [4] [5] [6] [7] DESCRIPTION PO1 (MAX6874 only). 0 = active low, 1 = active high. PO2 (MAX6874 only). 0 = active low, 1 = active high. PO3 (MAX6874)/PO1 (MAX6875). 0 = active low, 1 = active high. PO4 (MAX6874)/PO2 (MAX6875). 0 = active low, 1 = active high. PO5 (MAX6874)/PO3 (MAX6875). 0 = active low, 1 = active high. PO6 (MAX6874)/PO4 (MAX6875). 0 = active low, 1 = active high. PO7 (MAX6874)/PO5 (MAX6875). 0 = active low, 1 = active high. PO8 (MAX6874 only). 0 = active low, 1 = active high.
Table 16. PO_ Timeout Periods
REGISTER ADDRESS 11h 15h 1Ch 23h 2Ah 31h 35h 39h EEPROM MEMORY ADDRESS 8011h 8015h 801Ch 8023h 802Ah 8031h 8035h 8039h AFFECTED OUTPUTS BIT RANGE MAX6874 [3:1] [3:1] [4:2] [4:2] [3:1] [3:1] [3:1] [3:1] PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 MAX6875 -- -- PO1 PO2 PO3 PO4 PO5 -- 000 = 25s 001 = 1.5625ms 010 = 6.25ms 011 = 25ms 100 = 50ms 101 = 200ms 110 = 400ms 111 = 1600ms DESCRIPTION
ured by the user). To configure the MAX6874/ MAX6875, first apply an input voltage to IN1 or one of IN3-IN5 (MAX6874)/IN3-IN4 (MAX6875) (see the Powering the MAX6874/MAX6875 section). V IN1 > +4V or one of VIN3-VIN5 > +2.7V, to ensure device operation. Next, transmit data through the serial interface. Use the block write protocol to quickly configure the device. Write to the configuration registers first to ensure the device is configured properly. After completing the setup procedure, use the read word protocol to verify the data from the configuration registers. Lastly, use the write word protocol to write this data to the EEPROM registers. After completing EEPROM register configuration, apply full power to the system to begin normal operation. The nonvolatile EEPROM stores the latest configuration upon removal of power. Write 0's to all EEPROM registers to clear the memory.
Software Reboot A software reboot allows the user to restore the EEPROM configuration to the volatile registers without cycling the power supplies. Use the send byte command with data byte 88h to initiate a software reboot. The 3.5ms (max) power-up delay also applies after a software reboot. SMBus/I2C-Compatible Serial Interface The MAX6874/MAX6875 feature an I2C/SMBus-compatible serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL allow bidirectional communication between the MAX6874/MAX6875 and the master device at clock rates up to 400kHz. Figure 2 shows the interface timing diagram. The MAX6874/MAX6875 are transmit/receive slave-only devices, relying upon a master device to generate a clock signal. The master device (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer.
24
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
A master device communicates to the MAX6874/ MAX6875 by transmitting the proper address followed by command and/or data words. Each transmit sequence is framed by a START (S) or REPEATED START (SR) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is a logic input/opendrain output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7k for most applications. Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (Figure 3), otherwise the MAX6874/MAX6875 register a START or STOP condition (Figure 4) from the master. SDA and SCL idle high when the bus is not busy. Start and Stop Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START (S) condition (Figure 4) by transitioning SDA from high to low while SCL is high. The master device issues a STOP (P) condition (Figure 4) by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 7). Early STOP Conditions The MAX6874/MAX6875 recognize a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal I2C format. At least one clock pulse must separate any START and STOP condition.
MAX6874/MAX6875
SDA tBUF tSU:STA tLOW SCL tHIGH tHD:STA tR START CONDITION tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD:DAT tHD:STA tSU:STO
tSU:DAT
Figure 2. Serial-Interface Timing Details
SDA SDA
SCL SCL S P
DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID
START CONDITION
STOP CONDITION
Figure 3. Bit Transfer
Figure 4. Start and Stop Conditions 25
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Repeated START Conditions A REPEATED START (SR) condition may indicate a change of data direction on the bus. Such a change occurs when a command word is required to initiate a read operation (see Figure 7). SR may also be used when the bus master is writing to several I2C devices and does not want to relinquish control of the bus. The MAX6874/MAX6875 serial interface supports continuous write operations with or without an SR condition separating them. Continuous read operations require SR conditions because of the change in direction of data flow. Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The MAX6874/MAX6875 generate an ACK when receiving an address or data by pulling SDA low during the 9th clock period (Figure 5). When transmitting data, such as when the master device reads data back from the MAX6874/MAX6875, the MAX6874/MAX6875 wait for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. The MAX6874/MAX6875 generate a NACK after the slave address during a software reboot, while writing to the EEPROM, or when receiving an illegal memory address. Slave Address The MAX6874 slave address conforms to the following table:
SA7 (MSB) 1 SA6 0 SA5 1 SA4 0 SA3 A1 SA2 A0 SA1 X SA0 (LSB) R/W
X = Don't care.
The MAX6875 slave address conforms to the following table:
SA7 (MSB) 1 SA6 0 SA5 1 SA4 0 SA3 0 SA2 A0 SA1 X SA0 (LSB) R/W
X = Don't care.
SA7 through SA4 represent the standard interface address (1010) for devices with EEPROM. SA3 and SA2 correspond to the A1 and A0 address inputs of the MAX6874/MAX6875 (hardwired as logic low or logic high). A1 is internally set to 0 for the MAX6875. SA0 is a read/write flag bit (0 = write, 1 = read). The A0 and A1 address inputs allow up to four MAX6874s or two MAX6875s to connect to one bus. Connect A0 and A1 to GND or to the serial interface power supply (see Figure 6).
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGE
SCL
1
2
8
9
SDA BY TRANSMITTER
S SDA BY RECEIVER
Figure 5. Acknowledge 26 ______________________________________________________________________________________
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Send Byte The send byte protocol allows the master device to send one byte of data to the slave device (see Figure 7). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send an address that is not allowed. If the master sends 80h, 81h, or 82h, the data is ACK. This could be start of the write byte/word protocol, and the slave expects at least one further data byte. If the master sends a stop condition, the internal address pointer does not change. If the master sends 84h, this signifies that the block read protocol is expected, and a repeated start condition should follow. The device reboots if the master sends 88h. The send byte procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit data byte. 5) The addressed slave asserts an ACK on SDA. 6) The master sends a stop condition. Write Byte/Word The write byte/word protocol allows the master device to write a single byte in the register bank, preset an EEPROM (configuration or user) address for a subsequent read, or to write a single byte to the configuration or user EEPROM (see Figure 7). The write byte/word procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. The master sends an 8-bit command code. The addressed slave asserts an ACK on SDA. The master sends an 8-bit data byte. The addressed slave asserts an ACK on SDA. The master sends a stop condition or sends another 8-bit data byte. 9) The addressed slave asserts an ACK on SDA. 10) The master sends a stop condition. To write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. The command code must be in the range of 00h to 45h. The data byte is written to the register bank if the command code is valid. The slave generates a NACK at step 5 if the command code is invalid. To preset an EEPROM (configuration or user) address for a subsequent read, the 8-bit command code and a single 8-bit data byte are sent. The command code must be 80h if the write is to be directed into the configuration EEPROM, or 81h or 82h, if the write is to be directed into the user EEPROM. If the command code is 80h, the data byte must be in the range of 00h to 45h. If the command code is 81h or 82h, the data byte can be 00h to FFh. A NACK is generated in step 7 if none of the above conditions are true. To write a single byte of data to the user or configuration EEPROM, the 8-bit command code and a single 8-bit data byte are sent. The following 8-bit data byte is written to the addressed EEPROM location. 4) 5) 6) 7) 8)
MAX6874/MAX6875
SDA
1
0
1
0
A1 (0)
A0
X
R/W
ACK
START
MSB
LSB
SCL
(MAX6875 ONLY)
Figure 6. Slave Address ______________________________________________________________________________________ 27
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
SEND BYTE FORMAT S ADDRESS 7 bits WR 0 ACK DATA 8 bits Data Byte-presets the internal address pointer. ACK P WRITE WORD FORMAT S ADDRESS 7 bits WR 0 ACK COMMAND 8 bits Command Byte- MSB of the EEPROM register being written. ACK DATA 8 bits ACK DATA 8 bits ACK P
Slave Address- equivalent to chipselect line of a 3wire interface. RECEIVE BYTE FORMAT S ADDRESS 7 bits WR 1
Slave Address- equivalent to chipselect line of a 3wire interface. WRITE BYTE FORMAT
Data Byte-first byte is the LSB of the EEPROM address. Second byte is the actual data.
ACK
DATA 8 bits
ACK
P
S
ADDRESS 7 bits
WR 0
ACK
COMMAND 8 bits Command Byte- selects register being written.
ACK
DATA 8 bits
ACK
P
Slave Address- equivalent to chipselect line of a 3wire interface.
Data Byte-reads data from the register commanded by the last read byte or write byte transmission. Also dependent on a send byte.
Slave Address- equivalent to chipselect line of a 3wire interface.
Data Byte-data goes into the register set by the command byte if the command is below 50h. If the command is 80h, 81h, or 82h, the data byte presets the LSB of an EEPROM address. DATA BYTE N 8 bits
BLOCK WRITE FORMAT S ADDRESS 7 bits Slave Address- equivalent to chipselect line of a 3wire interface. BLOCK READ FORMAT S ADDRESS 7 bits WR 0 ACK COMMAND 84h Command Byte- prepares device for block operation. ACK SR ADDRESS 7 bits WR 1 ACK BYTE COUNT= 16 10h ACK DATA BYTE ACK 1 8 bits DATA BYTE ACK ... 8 bits DATA BYTE ACK N 8 bits P WR 0 ACK COMMAND ACK 83h Command Byte- prepares device for block operation. BYTE COUNT= N 8 bits ACK DATA BYTE 1 8 bits ACK DATA BYTE ... 8 bits ACK ACK P
Data Byte-data goes into the register set by the command byte.
Slave Address- equivalent to chipselect line of a 3wire interface.
Slave Address- equivalent to chipselect line of a 3wire interface.
Data Byte-data goes into the register set by the command byte.
S = Start condition. P = Stop condition.
Shaded = Slave transmission. SR = Repeated start condition.
Figure 7. SMBus/I2C Protocols
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Block Write The block write protocol allows the master device to write a block of data (1 to 16 bytes) to the EEPROM or to the register bank (see Figure 7). The destination address must already be set by the send byte or write byte protocol and the command code must be 83h. If the number of bytes to be written causes the address pointer to exceed 45h for the configuration register or configuration EEPROM, the address pointer stays at 45h, overwriting this memory address with the remaining bytes of data. The last data byte sent is stored at register address 45h. If the number of bytes to be written exceeds the address pointer FFh for the user EEPROM, the address pointer loops back to 00h, and continues writing bytes until all data is written. The block write procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends the 8-bit command code for block write (83h). 5) The addressed slave asserts an ACK on SDA. 6) The master sends the 8-bit byte count (1 to 16 bytes) N. 7) The addressed slave asserts an ACK on SDA. 8) The master sends 8 bits of data. 9) The addressed slave asserts an ACK on SDA. 10) Repeat steps 8 and 9 one time. 11) The master generates a stop condition. Receive Byte The receive byte protocol allows the master device to read the register content of the MAX6874/MAX6875 (see Figure 7). The EEPROM or register address must be preset with a send byte or write word protocol first. Once the read is complete, the internal pointer increases by one. Repeating the receive byte protocol reads the contents of the next address. The receive byte procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a read bit (high). 3) The addressed slave asserts an ACK on SDA. 4) The slave sends 8 data bits. 5) The master asserts a NACK on SDA. 6) The master generates a stop condition. Block Read The block read protocol allows the master device to read a block of 16 bytes from the EEPROM or register bank (see Figure 7). Read fewer than 16 bytes of data by issuing an early STOP condition from the master, or by generating a NACK with the master. The send byte or write byte protocol predetermines the destination address with a command code of 84h. The block read procedure follows: 1) The master sends a start condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends 8 bits of the block read command (84h). 5) The slave asserts an ACK on SDA, unless busy. 6) The master generates a repeated start condition. 7) The master sends the 7-bit slave address and a read bit (high). 8) The slave asserts an ACK on SDA. 9) The slave sends the 8-bit byte count (16). 10) The master asserts an ACK on SDA. 11) The slave sends 8 bits of data. 12) The master asserts an ACK on SDA. 13) Repeat steps 8 and 9 fifteen times. 14) The master generates a stop condition. Address Pointers Use the send byte protocol to set the register address pointers before read and write operations. For the configuration registers, valid address pointers range from 00h to 45h. Register addresses outside of this range result in a NACK being issued from the MAX6874/ MAX6875. When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 45h. If the address pointer is already 45h, and more data bytes are being sent, these subsequent bytes overwrite address 45h repeatedly, leaving only the last data byte sent stored at this register address.
MAX6874/MAX6875
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
For the configuration EEPROM, valid address pointers range from 8000h to 8045h. Registers 8046h to 804Fh are reserved and should not be overwritten. Register addresses from 8050h to 80FFh return a NACK from the MAX6874/MAX6875. When using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 8045h. If the address pointer is already 8045h, and more data bytes are being sent, these subsequent bytes overwrite address 8045h repeatedly, leaving only the last data byte sent stored at this register address. For the user EEPROM, valid address pointers range from 8100h to 81FFh and 8200h to 82FFh. Block write and block read protocols allow the address pointer to reset (to 8100h or 8200h) when attempting to write or read beyond 81FFh or 82FFh. time after power-up or software reboot. Write commands to the configuration EEPROM are allowed at any time after power-up or software reboot, unless the configuration lock bit is set (see Table 20). The maximum cycle time to write a single byte is 11ms (max).
User EEPROM
The 512 byte user EEPROM addresses range from 8100h to 82FFh (see Figure 7). Store software-revision data, board-revision data, and other data in these registers. The maximum cycle time to write a single byte is 11ms (max). Configuration Register Bank and EEPROM The configuration registers can be directly modified by the serial interface without modifying the EEPROM after the power-up procedure terminates and the configuration EEPROM data has been loaded into the configuration register bank. Use the write byte or block write protocols to write directly to the configuration registers. Changes to the configuration registers take effect immediately and are lost upon power removal. At device power-up, the register bank loads configuration data from the EEPROM. Configuration data may be directly altered in the register bank during application development, allowing maximum flexibility. Transfer the new configuration data, byte by byte, to the configuration EEPROM with the write byte protocol. The next device power-up or software reboot automatically loads the new configuration.
Configuration EEPROM
The configuration EEPROM addresses range from 8000h to 8045h. Write data to the configuration EEPROM to automatically set up the MAX6874/MAX6875 upon powerup. Data transfers from the configuration EEPROM to the configuration registers when ABP exceeds UVLO during power-up or after a software reboot. After ABP exceeds UVLO, an internal 1MHz clock starts after a 5s delay, and data transfer begins. Data transfer disables access to the configuration registers and EEPROM. The data transfer from EEPROM to configuration registers takes 3.5ms (max). Read configuration EEPROM data at any
Table 17. Register Map
REGISTER ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah EEPROM MEMORY ADDRESS 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h 8009h 800Ah READ/ WRITE R/W R/W R/W R/W R/W R/W -- -- -- -- -- DESCRIPTION IN1 undervoltage detector threshold (Table 2). IN2 undervoltage detector threshold (Table 3). IN3 undervoltage detector threshold (Table 4). IN4 undervoltage detector threshold (Table 4). IN5 undervoltage detector threshold (MAX6874 only) (Table 4). IN6 undervoltage detector threshold (MAX6874 only) (Table 4). Not used. Not used. Not used. Not used. Not used.
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Table 17. Register Map (continued)
REGISTER ADDRESS 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch EEPROM MEMORY ADDRESS 800Bh 800Ch 800Dh 800Eh 800Fh 8010h 8011h 8012h 8013h 8014h 8015h 8016h 8017h 8018h 8019h 801Ah 801Bh 801Ch 801Dh 801Eh 801Fh 8020h 8021h 8022h 8023h 8024h 8025h 8026h 8027h 8028h 8029h 802Ah 802Bh 802Ch READ/ WRITE -- -- R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Not used. Not used. Threshold range selection (Tables 2-4). PO1 (MAX6874 only) input selection (Table 7). PO1 (MAX6874 only) input selection (Table 7). PO1 (MAX6874 only) input selection (Table 7). PO1 (MAX6874 only) input selection, PO_ timeout period, and output type selection (Tables 7, 16). PO2 (MAX6874 only) input selection (Table 8). PO2 (MAX6874 only) input selection (Table 8). PO2 (MAX6874 only) input selection (Table 8). PO2 (MAX6874 only) input selection and PO_ timeout period (Tables 8, 16). PO3 (MAX6874)/PO1 (MAX6875) input selection (Table 9). PO3 (MAX6874)/PO1 (MAX6875) input selection (Table 9). PO3 (MAX6874)/PO1 (MAX6875) input selection (Table 9). Set to 0. Set to 0. Set to 0. PO3 (MAX6874)/PO1 (MAX6875) input selection and PO_ timeout period (Tables 9, 16). PO4 (MAX6874)/PO2 (MAX6875) input selection (Table 10). PO4 (MAX6874)/PO2 (MAX6875) input selection (Table 10). PO4 (MAX6874)/PO2 (MAX6875) input selection (Table 10). Set to 0. Set to 0. Set to 0. PO4 (MAX6874)/PO2 (MAX6875) input selection and PO_ timeout period (Tables 6, 18). PO5 (MAX6874)/PO3 (MAX6875) input selection (Table 11). PO5 (MAX6874)/PO3 (MAX6875) input selection (Table 11). PO5 (MAX6874)/PO3 (MAX6875) input selection (Table 11). Set to 0. Set to 0. Set to 0. PO5 (MAX6874)/PO3 (MAX6875) input selection and PO_ timeout period (Tables 11, 18). PO6 (MAX6874)/PO4 (MAX6875) input selection (Table 12). PO6 (MAX6874)/PO4 (MAX6875) input selection (Table 12). DESCRIPTION
MAX6874/MAX6875
31
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 17. Register Map (continued)
REGISTER ADDRESS 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h EEPROM MEMORY ADDRESS 802Dh 802Eh 802Fh 8030h 8031h 8032h 8033h 8034h 8035h 8036h 8037h 8038h 8039h 803Ah 803Bh 803Ch 803Dh 803Eh 803Fh 8040h 8041h 8042h 8043h 8044h 8045h READ/ WRITE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W -- R/W DESCRIPTION PO6 (MAX6874)/PO4 (MAX6875) input selection (Table 12). Set to 0. Set to 0. Set to 0. PO6 (MAX6874)/PO4 (MAX6875) input selection and PO_ reset timeout period (Tables 12, 16). PO7 (MAX6874)/PO5 (MAX6875) input selection (Table 13). PO7 (MAX6874)/PO5 (MAX6875) input selection (Table 13). PO7 (MAX6874)/PO5 (MAX6875) input selection (Table 13). PO7 (MAX6874)/PO5 (MAX6875) input selection and PO_ timeout period (Tables 13, 16). PO8 (MAX6874 only) input selection (Table 14). PO8 (MAX6874 only) input selection (Table 14). PO8 (MAX6874 only) input selection (Table 14). PO8 (MAX6874 only) input selection and PO_ timeout period (Tables 14, 16). Programmable output polarity (active high/active low) (Table 15). GPI_ input polarity, PO5, PO6 (Table 5). WD input selection and timeout enable (Table 18). WD initial and normal timeout duration (Table 19). Must be set to 0. Must be set to 0. MR input and programmable output behavior (Table 6). Must be set to 0. Must be set to 0. User EEPROM write disable (Table 21). Reserved. Should not be overwritten. Configuration lock (Table 20).
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
REGISTER BANK 00h CONFIGURATION DATA 45h 8045h 8000h CONFIGURATION EEPROM 8100h USER EEPROM 8200h USER EEPROM
81FFh
82FFh
Figure 8. Memory Map
Table 18. Watchdog Inputs
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE Watchdog Input Selection: 00 = GPI1 01 = GPI2 10 = GPI3 11 = GPI4 (MAX6874 only) Watchdog Internal Input Selection: 000 = PO1 (MAX6874), not used (MAX6875) 001 = PO2 (MAX6874), not used (MAX6875) 010 = PO3 (MAX6874), PO1 (MAX6875) 011 = PO4 (MAX6874), PO2 (MAX6875) 100 = PO5 (MAX6874), PO3 (MAX6875) 101 = PO6 (MAX6874), PO4 (MAX6875) 110 = PO7 (MAX6874), PO5 (MAX6875) 111 = PO8 (MAX6874), not used (MAX6875) Watchdog Dependency on Inputs: 00 = 11 = Watchdog clear depends on both GPI_ from 3Ch[1:0] and PO_ from 3Ch[4:2]. 01 = Watchdog clear depends only on PO_ from 3Ch[4:2]. 10 = Watchdog clear depends only on GPI_ from 3Ch[1:0]. Must be set to 1 DESCRIPTION
[1:0]
3Ch
803Ch
[4:2]
[6:5]
[7]
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Table 19. Watchdog Timeout Period Selection
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE Normal Watchdog Timeout Period: 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s Initial Watchdog Timeout Period (immediately following power-up, reset event, or enabling watchdog): 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s Watchdog Enable: 0 = Disables watchdog timer 1 = Enables watchdog timer Not used DESCRIPTION
[2:0]
3Dh
803Dh [5:3]
[6] [7]
Configuring the Watchdog Timer (Registers 3Ch-3Dh) A watchdog timer monitors microprocessor (P) software execution for a stalled condition and resets the P if it stalls. The output of a watchdog timer (one of the programmable outputs) connects to the reset input or a nonmaskable interrupt of the P. Registers 3Ch-3Dh configure the watchdog functionality of the MAX6874/MAX6875. Program the watchdog timer to assert one or more programmable outputs (see Tables 7-14). Program the watchdog timer to reset on one of the GPI_ inputs, one of the programmable outputs, or a combination of one GPI_ input and one programmable output. The watchdog timer features independent initial and normal watchdog timeout periods. The initial watchdog timeout period applies immediately after power-up, after a reset event takes place, or after enabling the watchdog timer. The initial watchdog timeout period allows the P to perform its initialization process. If no pulse occurs during the initial watchdog timeout period, the P is taking too long to initialize, indicating a potential problem.
34
The normal watchdog timeout period applies in every other cycle after the initial watchdog timeout period occurs. The normal watchdog timeout period monitors a pulsed output of the P that indicates when normal processor behavior occurs. If no pulse occurs during the normal watchdog timeout period, this indicates that the processor has stopped operating or is stuck in an infinite execution loop. Register 3Dh programs the initial and normal watchdog timeout periods, and enables or disables the watchdog timer. See Tables 18 and 19 for a summary of the watchdog behavior. Configuration Lock Lock the configuration register bank and configuration EEPROM contents after initial programming by setting the lock bit high (see Table 20). Locking the configuration prevents write operations to all registers except the configuration lock register. Clear the lock bit to reconfigure the device.
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EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Table 20. Configuration Lock Register
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [7:1] 0 = configuration unlocked. 1 = configuration locked. Not used. DESCRIPTION
MAX6874/MAX6875
45h
8045h
Table 21. Write Disable Register
REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [0] [1] [2] [3] 43h 8043h [4] [5] [6] [7] 0 = write not disabled if PO5 (MAX6874)/PO3 (MAX6875) asserts. 1 = write disabled if PO5 (MAX6874)/PO3 (MAX6875) asserts. 0 = write not disabled if PO6 (MAX6874)/PO4 (MAX6875) asserts. 1 = write disabled if PO6 (MAX6874)/PO4 (MAX6875) asserts. 0 = write not disabled if PO7 (MAX6874)/PO5 (MAX6875) asserts. 1 = write disabled if PO7 (MAX6874)/PO5 (MAX6875) asserts. 0 = write not disabled if PO8 asserts (MAX6874). 1 = write disabled if PO8 asserts (MAX6874). Set to 0 (MAX6875). DESCRIPTION 0 = write not disabled if PO1 asserts (MAX6874). 1 = write disabled if PO1 asserts (MAX6874). Set to 0 (MAX6875). 0 = write not disabled if PO2 asserts (MAX6874). 1 = write disabled if PO2 asserts (MAX6874). Set to 0 (MAX6875). 0 = write not disabled if PO3 (MAX6874)/PO1 (MAX6875) asserts. 1 = write disabled if PO3 (MAX6874)/PO1 (MAX6875) asserts. 0 = write not disabled if PO4 (MAX6874)/PO2 (MAX6875) asserts. 1 = write disabled if PO4 (MAX6874)/PO2 (MAX6875) asserts.
Write Disable A unique write disable feature protects the MAX6874/ MAX6875 from inadvertent user EEPROM writes. As input voltages that power the serial interface, a P, or any other writing devices fall, unintentional data may be written onto the data bus. The user EEPROM write disable function (see Table 21) ensures that unintentional data does not corrupt the MAX6874/MAX6875 EEPROM data.
tion. The local volatile memory latches lose their contents at power-down. Therefore, at power-up, the device configuration must be restored by downloading the contents of the EEPROM (non-volatile memory) to the local latches. This download occurs in a number of steps: 1) Programmable outputs go high impedance with no power applied to the device. 2) When ABP exceeds +1V, all programmable outputs are weakly pulled to GND through a 10A current sink. 3) When ABP exceeds UVLO, the configuration EEPROM starts to download its contents to the volatile configuration registers. The programmable outputs assume their programmed conditional output state when download is complete.
35
Applications Information
Configuration Download at Power-up
The configuration of the MAX6874/MAX6875 (undervoltage thresholds, PO_ timeout periods, watchdog behavior, programmable output conditions, etc.) depends on the contents of the EEPROM. The EEPROM is comprised of buffered latches that store the configura-
______________________________________________________________________________________
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
4) Any attempt to communicate with the device prior to this download completion results in a NACK being issued from the MAX6874/MAX6875. Other Fault Signals from C Connect a general-purpose output from a C to one of the GPI_ inputs to allow interrupts to assert any output of the MAX6874/MAX6875. Configure one of the programmable outputs to assert on whichever GPI_ input connects to the general purpose output of the C.
Forcing Programmable Outputs High During Power-Up
A weak 10A pulldown holds all programmable outputs low during power-up until ABP exceeds the undervoltage lockout (UVLO) threshold. Applications requiring a guaranteed high programmable output for ABP down to GND require external pullup resistors to maintain the logic state until ABP exceeds UVLO. Use 20k resistors for most applications.
Layout and Bypassing
For better noise immunity, bypass each of the voltage detector inputs to GND with 0.1F capacitors installed as close to the device as possible. Bypass ABP and DBP to GND with 1F capacitors installed as close to the device as possible. ABP and DBP are internally generated voltages and should not be used to supply power to external circuitry.
Uses for General-Purpose Inputs (GPI1-GPI4)
Watchdog Timer Program GPI_ as an input to the watchdog timer in the MAX6874/MAX6875. The GPI_ input must toggle within the watchdog timeout period, otherwise any programmable output dependent on the watchdog timer asserts. Additional Manual Reset Functions Program PO7 (MAX6874)/PO5 (MAX6875) to depend on one of the GPI_ inputs. Any output that depends on GPI_ asserts when GPI_ is held in its active state, effectively acting as a manual reset input.
Configuration Latency Period
A delay of less than 5s occurs between writing to the configuration registers and the time when these changes actually take place, except when changing one of the voltage-detector thresholds. Changing a voltage-detector threshold typically takes 150s. When changing EEPROM contents, a software reboot or cycling of power is required for these changes to transfer to volatile memory.
Chip Information
PROCESS: BiCMOS
36
______________________________________________________________________________________
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Pin Configurations
TOP VIEW
N.C. I.C. N.C. IN2 IN3 IN4
IN1
MAX6874/MAX6875
32
31
30
29
28
27
26
25
32
31
30
29
28
27
PO2 PO3 PO4 GND PO5 PO6 PO7 PO8
1 2 3 4 5 6 7 8 10 *EXPOSED PADDLE
24 23 22 21
N.C. N.C. DBP ABP GPI1 GPI2 GPI3 GPI4
26
25 24 23 22 21
N.C.
PO1
I.C.
IN2
IN3
IN4
IN5
IN1
IN6
N.C. PO1 PO2 GND PO3 PO4 PO5 N.C.
1 2 3 4 5 6 7 8 10 *EXPOSED PADDLE
N.C. N.C. DBP ABP GPI1 GPI2 GPI3 N.C.
MAX6874
20 19 18 17
MAX6875
20 19 18 17
11
12
13
14
15
16
11
12
13
14
15
A0
MARGIN
SCL
MR
N.C.
N.C.
SDA
A0
A1
MARGIN
SCL
N.C.
(7mm x 7mm Thin QFN)
*EXPOSED PADDLE INTERNALLY CONNECTED TO GND.
(7mm x 7mm Thin QFN)
N.C.
SDA
Selector Guide
PART MAX6874ETJ MAX6875ETJ VOLTAGE-DETECTOR INPUTS 6 4 GENERAL-PURPOSE INPUTS 4 3 PROGRAMMABLE OUTPUTS 8 5
______________________________________________________________________________________
N.C.
MR
16
9
9
37
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Typical Operating Circuit
+12V DC-DC 1 DC-DC 2 DC-DC 3 DC-DC 4 +12V +5V +3.3V +2.5V +0.7V
IN1 MARGIN MR ABP
PO1
IN3
PO2
IN4
PO3
IN5
PO4
IN6 SDA SCL PO5
RPU
RPU P SDA SCL RESET NMI, WD ALERT LOGIC OUTPUT
MAX6874
DBP GND GPI2 GPI3 GPI4
PO6 GPI1 (WD) A0 A1
+12V SUPPLY PO1 +5V SUPPLY PO2 +2.5V SUPPLY PO3 +3.3V SUPPLY PO4 +0.7V SUPPLY PO5 tPO1
+12V BUS INPUT ENABLE +5V DC-DC CONVERTER +5V OUTPUT tPO2 ENABLE +2.5V DC-DC CONVERTER +2.5V OUTPUT tPO3 ENABLE +3.3V DC-DC CONVERTER +3.3V OUTPUT tPO4 ENABLE +0.7V DC-DC CONVERTER +0.7V OUTPUT tPO5 SYSTEM RESET
38
______________________________________________________________________________________
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX6874/MAX6875
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k L DETAIL A e (ND-1) X e DETAIL B
e L
C L
C L
L1
L
L
e
e
A1
A2
A
TITLE:
SEMICONDUCTOR
PROPRIETARY INFORMATION
DALLAS
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
D
1
2
______________________________________________________________________________________
32, 44, 48L QFN.EPS
39
EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors MAX6874/MAX6875
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0144
D
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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